1. Field of the Invention
The present invention generally relates to a method of manufacturing a self-aligned, lightly-doped drain (LDD) field effect transistor, and more particularly to a method for producing inverse T-gate LDD structures with sub-micron channel lengths and fully self-aligned features, including source and drain contacts.
2. Description of the Prior Art
The advantages of LDD inverse T-gate field effect transistor structures are well known in the art and there have been a number of proposals in the prior art relating to such devices and their fabrication.
Japanese patent number 1-206667 dated Aug. 18, 1989 discloses a transistor gate electrode equipped with a two-layer structure, wherein a lower gate electrode has a higher etching selectivity in a reactive ion etching process than an upper gate electrode, and the lower gate electrode is equipped with a film 500 angstroms or less in thickness allowing ion implantation therethrough. As compared with the upper gate electrode, the lower gate electrode is designed to expand in the MOS transistor channel direction, and to be shaped as inverted T.
U.S. Pat. No. 4,963,504 to Huang, entitled "Method for Fabricating Double Implanted LDD Transistor Self-Aligned With Gate", discloses a double implanted and aligned LDD transistor comprising a gate having a central alignment member and a pair of outboard alignment members having portions contiguous with the gate oxide layer. A lightly-doped junction is aligned with the central alignment member and a heavily doped junction is aligned with the outboard alignment members.
U.S. Pat. No. 4,939,154 to Shimbo, entitled "Method of Fabricating An Insulated Gate Semiconductor Device Having a Self-Aligned Gate", discloses a fabrication method for miniature insulated gate semiconductor devices, such as MOS and CMOS devices, in which their gates are formed by self-alignment with a lightly-doped drain (LDD) structure.
The following patents also disclose various LLD structures and fabrication methods.
U.S. Pat. No. 4,818,715 to Chao, entitled "Method of Fabricating a LDDFET With Self-Aligned Silicide".
U.S. Pat. No. 4,728,617 to Woo et al., entitled "Method of Fabricating a MOSFET With Graded Source and Drain Regions".
U.S. Pat. No. 4,889,827 to Willer, entitled "Method For The Manufacture of a MOSFET Comprising Self-Aligned Gate".
U.S. Pat. No. 3,438,121 to Wanlass et al., entitled "Method of Making a Phosphorous-Protected Semiconductor Device".
U.S. Pat. No. 4,929,567 to Park et al., entitled "Method of Manufacturing a Self-Aligned GaAs MOSFET with T Type Tungsten Gate".
U.S. Pat. No. 4,927,782 to Davey et al., entitled "Method of Making Self-Aligned GaAs/AlGaAs FETs".
U.S. Pat. No. 4,906,589 to Chao, entitled "Inverse-T LDDFET With Self-Aligned Silicide".